Join us on Thursday, October 29, for our Practical #LLM Techniques for #FPGA Functional Verification webinar. See the full agenda and register here aldec.com/en/company/events.
#EDA
#FPGAverification
#LargeLanguageModels
#VHDL
#SystemVerilog
Join us on November 12 for our Modeling #AMD #Zynq MPSoC PS8 Interfaces with #OSVVM webinar. You can see the full agenda and register here aldec.com/en/company/events
#EDA #FPGA #FPGAverification #AMDVivado
#Vivado
Join us on October 29 for our Practical #LLMTechniques for #FPGA #FunctionalVerification webinar. We’ll be live at 16:00 CEST and at 11:00 PDT. aldec.com/en/company/events
#AI #ArtificialIntelligence #LargeLanguageModels
#GenerativeAI #EDA #FPGAVerification #FPGAdesign
Our Practical #CoSimulationTechniques with #OSVVM webinar series concludes on Thursday, September 24. We will explore how complex protocol VCs can be constructed, using the new #PCIe co-simulation VC as a practical case study. aldec.com/en/company/events
#VHDL
It’s just a little over month before the three-day #DO254 #ED80 practitioner’s course will be held in Guildford, United Kingdom, from October 20 to 22. See the agenda here aldec.com/en/company/events.
#AirborneHardware
#SafetyCritical
#DesignAssurance
#AvionicsCertification
Our Practical #CoSimulation Techniques with #OSVVM webinar series concludes on Thursday, September 24. Agenda and registration details here aldec.com/en/company/events
#EDA
#FPGA
#Altera
#AlteraFPGA
#PCIe
#FPGAsimulation
#RivieraPRO
We are pleased to draw your attention to Efinix’s hands-on workshop in Grand Rapids, Michigan, on Tuesday, September 15. Details and registration here: forms.cloud.microsoft/r/6gb9…
#Efinix
#EfinixFPGA
#EDA
#FPGA
#ActiveHDL
There’s still time to register for this week’s webinar on Thursday, September 3 - Practical Co-Simulation Techniques with #OSVVM Part 2: #RISCV Software and Logic CoDevelopment. aldec.com/en/company/events
#EDA
#VHDL
#FPGA
#FPGAsimulation
Join us on September 3 at 16:00 CEST or 11:00 PDT for our Practical Co-Simulation Techniques with #OSVVM Part 2: #RISCV Software and Logic CoDevelopment webinar. Register here aldec.com/en/company/events
#EDA
#VHDL
#FPGA
#FPGAsimulation
Join us on Thursday (August 20) for Getting Started with #OSVVM #CoSimulation, the first webinar in our three-part Practical Co-Simulation Techniques series. aldec.com/en/company/events
#EDA
#HDL
#HDLsimulation
#VHDL
#FPGA
#FPGAdesign
#FPGAsimulation
#FPGAverification
Designed to provide a comprehensive understanding of #DO254 specification, objectives and requirements for #airbornehardwaredevelopment, the DO-254 (ED-80) Practitioner’s Course will be held in Guildford, UK, from October 20 to 22. aldec.com/en/company/events
Check out our latest tutorial video, Simulating Efinix IP and Designs with Active-HDL. aldec.com/en/support/resourc…
#Efinix
#EfinixFPGA
#FPGA
#FPGAdesign
#FPGAsimulation
#FPGAverification
#EDA
Registration is open for the #DO254(ED-80) Practitioner’s Course - October 20 to 22 – in Guildford, United Kingdom. Learn about the specification, its objectives and the complete hardware lifecycle. aldec.com/en/company/events
#EDA
#DesignAssurance
#AerospaceEngineering
Join us on August 20, at 16:00 CEST or 11:00 PST, for part 1 of our 3-part “Practical Co-Simulation Techniques With #OSVVM” webinar series. Learn how co-simulation fits into the OSVVM framework and lots more. aldec.com/en/company/events
#EDA
#VHDL
#FPGA
#FPGAsimulation
The AXI-Based Design & Verification webinar on Thursday, June 24, will cover the basics of on-chip buses and provide an overview of the #AMBA #AXI3 AXI bus architecture. See the full agenda and register here aldec.com/en/company/events
#EDA
#BusArchitecture
#ARM
Registration is now open for our three-part Practical #CoSimulation Techniques with #OSVVM webinar series. See the three agendas and register here aldec.com/en/company/events
#VHDL #EDA #FPGA #FPGAdesign #FPGAsimulation
Riviera-PRO release adds AI Assistant, an #AI companion powered by AI models delivered by major #LLMproviders. Find out more about Riviera-PRO and request a free evaluation license here aldec.com/en/rtl-simulator
#RTLsimulation #FPGA #EDA #RivieraPRO
Registration is now open for Doulos’s June 24 webinar. Topics to be covered include the basics of on-chip buses and an overview of the #AMBA #AXI3: AXI bus architecture. See the full agenda and register here aldec.com/en/company/events
#EDA
#BusArchitecture
#ARM
Join us this Thursday, June 4, for part 2 of ‘Making a Simple VHDL Testbench Step-by-Step’ in which we will introduce register access and Bus Functional Models (BFMs). Register here aldec.com/en/company/events
#UVVM
#VHDL
#EDA
#Testbench
#FPGA
#FPGAdesign
We are pleased to announce the immediate availability of Active-HDL release version 17.0.
#ActiveHDL #FPGA #EDA #OSVVM #VHDL #SystemVerilog #UVVM
