My key takeaways from the $INTC Intel Foundry interview by Dwarkesh Chris Auth made it clear that 14A is already well into development. He said the node has been in the works for more than three years and is now close to locking the process and the tool set. There are roughly two thousand steps that still need fine tuning so the factory can run thousands of wafers a week with consistent results. What I found useful was how directly he connected this to the 10nm experience. He described how that node carried aggressive targets and tried to scale faster than the tools allowed, which created a heavy load on both the process and the engineers. It eventually delivered strong yield, performance, and cost, but the schedule slip was expensive. The approach now is to use formal phase gates and maturity metrics so the team does not try to force too much new technology into a single node if it threatens the timeline customers need. On High NA EUV specifically, Auth said it is available as an option in the 14A PDK and that the company is having separate discussions with customers about whether they want to use it. The most concrete competitive point for me was Auth’s explanation of why High NA EUV works for Intel in a way it does not for TSMC. He said: “High NA’s a good example of where, because of the architecture of our technology versus TSMC’s, we make different conclusions off of the same tool set. We use backside power. That means that you actually alleviate some of the pitch requirements you have on the front side. That allows you to print that directly with High NA. TSMC has to run tighter pitches because they don’t have backside power, and they can’t do that with High NA, so they have to use double patterning EUV. So for them, it’s not very helpful. For us, it is very helpful.” The tool itself is expensive and can print smaller features in a single pass, but the economic case depends on how many multi patterning steps it actually removes. With backside power already in place, Intel can use a single exposure on critical layers. Without it, TSMC still faces pitches that require multiple passes even with High NA. That architectural difference is what makes the same machine a clearer win for Intel. Intel CTO Pushkar Ranade’s comments on demand and capacity were the clearest statement of the constraint the whole industry is facing. He described current AI requirements as running well above installed capacity, and he noted that individual hyperscalers and model companies have enough demand to fill an entire fab or more. The limiter is tools. ASML is producing fewer than one hundred EUV machines a year and does not plan a large increase even by the end of the decade. Other equipment is also tight, and once a process is locked to a specific tool there is little flexibility to switch suppliers. Ranade said that even with unlimited capital the existing global tool stock would probably support something closer to a doubling of leading edge wafer output rather than a much larger increase. He pointed out that roughly eighty percent of the tool set can carry over from 18A to 14A, with the rest new for denser geometry, and that further yield gains get harder once a process is already well tuned. On the cost structure he was direct: once a fab is built, about eighty percent of the cost is fixed, so every extra point of utilization or yield matters a great deal. That is also why the industry has consolidated so sharply. He said there are now only three foundries left at the advanced node, down from roughly twenty forty years ago, because many companies simply stopped manufacturing as the fixed costs rose. On the question of catching TSMC, Pushkar drew a clear line between technology and scale. He said: “Catching up to TSMC has multiple facets. The catch up that we need to do is in scale. Like you said, they’re just a much larger wafer manufacturer today than we are, and even bigger than what Samsung is. Catching up in scale will be a gradual process. If you meant catching up in terms of just the technology, I think we’re already there. We might be a few percent off on performance or power or area density. But this sort of benchmarking, where one foundry is ahead or one foundry is behind, makes sense when you’re a whole generation behind or two generations behind or ahead. That’s when it makes a meaningful difference in your die output or your die area or functionality like power. But if you’re within a few percent, you’re splitting hairs at that point in time, because it’s not very unidimensional. It’s not just about density, it’s not just about raw performance. Different applications require different vectors. You can be off by a few percent, but you need to be on time. Your execution needs to be such that your yields are very high to support very large and very rapid ramps. That actually is more important than catching up on a few percent in performance or area.” He added that Intel builds multiple transistor types, different SRAM variants, and analog and RF circuits, so the real measure is the full set of capabilities rather than a single density number. He also noted that Capex is currently lower than TSMC’s because Intel has operated more as an integrated manufacturer, but that this will change as external foundry volume increases. With today’s demand visible, he said the company would have bought more tools earlier and expects to invest more now. The closing discussion on Terafab reinforced the demand point. Ranade referenced Musk’s view that the companies involved either build the fab or they do not have the chips they need. Intel is working with them to help accelerate what is an extremely complex manufacturing flow. He observed that tool shortages mean a new fab does not automatically expand global silicon supply by its full capacity, but additional clean room space is still required and other inputs such as power and water can be scaled more easily. The conversation also touched on whether the industry’s caution around large capital commitments has locked in certain practices around clean rooms and process flows that might be worth revisiting. For me, Terafab reads as a large external demand signal for advanced U.S. capacity at a time when AI requirements already exceed what current tool stocks can support. Overall, the interview left me with the sense that Intel is applying tighter schedule discipline after 10nm, using backside power to make High NA EUV economically viable in a way TSMC cannot yet match, and treating technology parity as largely achieved while the remaining work is scale and execution. With only three companies still running advanced nodes, those differences in process architecture and domestic capacity are more relevant than they would have been in a less consolidated industry.