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RISC-V Instructions

@ItsABitRISCV

Tweets about the RISC-V Instruction Set Architecture (ISA). #riscv Not affiliated with RISC-V International.

 Earth & Low Orbit
Joined May 2020
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Photo by RISC-V Instructions (@ItsABitRISCV)Photo by RISC-V Instructions (@ItsABitRISCV)Photo by RISC-V Instructions (@ItsABitRISCV)Photo by RISC-V Instructions (@ItsABitRISCV)Photo by RISC-V Instructions (@ItsABitRISCV)Photo by RISC-V Instructions (@ItsABitRISCV)Photo by RISC-V Instructions (@ItsABitRISCV)Photo by RISC-V Instructions (@ItsABitRISCV)Photo by RISC-V Instructions (@ItsABitRISCV)
When they want to build $350 XR headsets and not $3500 ones? 🙃
Ziliang Peng 🏴‍☠️ (@cyberpengk) profile pictureZiliang Peng 🏴‍☠️
@cyberpengk4 Jun 2023
When will Apple move chip architecture to RISC-V?
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RISC-V Instructions retweeted
Sally Ward-Foxton (@sallywf) profile picture
Sally Ward-Foxton@sallywf5 Jun 2023
The next gen Xcore will be compatible with RISC-V (but is not a RISC-V core). "It became obvious RISC-V is here to stay and that our customers would value... all the tools and facilities that came along with it." #ai #xcore #xmos #edgeai #aiot #riscv eetimes.com/xmos-joins-risc-…

XMOS Joins RISC-V Ecosystem - EE Times

The British software-defined SoC maker has made its latest-gen core RISC-V compatible.

eetimes.com
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RISC-V Instructions retweeted
RISC-V International (@risc_v) profile picture
RISC-V International
@risc_v5 Jun 2023
📍Barcelona, Spain #RISCVSUMMITEUROPE starts tomorrow! Will you be joining us? #RISCV #RISCVEverywhere
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RISC-V Instructions retweeted
MIPS (@mips_riscv) profile picture
MIPS
@mips_riscv5 Jun 2023
Calling all RISC-V Summit Europe attendees! Stop by Booth 10 in Meeting Room 5+6 to learn more about MIPS' eVocore IP cores so you can have the scalability and configurability you need to meet your specific application requirements. #cpus #riscvsummiteurope #mips #riscv
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RISC-V Instructions retweeted
eeNews Europe (@eeNewsEurope) profile picture
eeNews Europe
@eeNewsEurope5 Jun 2023
Complete RISC-V analog IP subsystem targets IoT // eenewseurope.com/en/complete… @AgileAnalog @risc_v @Calista_Redmond
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RISC-V Instructions retweeted
Tom's Hardware (@tomshardware) profile picture
Tom's Hardware@tomshardware5 Jun 2023
Newly Revealed RISC-V Vector Unit Could Be Used for AI, HPC, GPU Applications trib.al/UBJNxeU
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Isn't that what people did with Arm for the first decade? kek
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RISC-V Instructions retweeted
Linux.com (@linuxdotcom) profile picture
Linux.com@linuxdotcom5 Jun 2023
Linux Foundation & RISC-V International Launch RISC-V Fundamentals Course - linux.com/news/linux-foundat…
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RISC-V Instructions retweeted
embedded.com (@embedded_online) profile picture
embedded.com
@embedded_online26 May 2023
SiFive donates WorldGuard open model to enable security on RISC-V embedded.com/sifive-donates-…
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RISC-V Instructions retweeted
PlatformIO (@PlatformIO_Org) profile picture
PlatformIO@PlatformIO_Org8 May 2023
#LearnEmbedded 🎓 "PlatformIO Labs Helps Imagination Technologies Improve RISC-V Computer Architecture Training" The new course removes barriers while working with RISC-V IP Cores and FPGAs 👉 piolabs.com/blog/press-relea… 📌 #OpenSource #EmbeddedSystems #Electronics #Semiconductor
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RISC-V Instructions retweeted
RISC-V International (@risc_v) profile picture
RISC-V International
@risc_v8 May 2023
Come visit the #RISCV Zone at @60thDAC, taking place from July 9-13 in Moscone West, San Francisco! Learn more and register here: hubs.ly/Q01NH8pq0 #RISCVeverywhere
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#VLSI2023 Circuits Highlight C3-4 Power of the end-to-end system w/o image sensor is 0.62 & 1.61mW for 2 and 15fps, respectively. Figure: An SoC prototype comprised of a DCIM-base Deep Learning accelerator, RISC-V microprocessor, & interface for off-chip image sensor connection.
Image from IEEE Symposium on VLSI Technology and Circuits (@VLSI_2026)
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RISC-V International (@risc_v) profile picture
RISC-V International
@risc_v8 May 2023
Applications for our #RISCV summer #mentorship program are open! We have four available positions, including one non-technical role. Apply by Monday, May 15: hubs.la/Q01NHnfX0 #RISCVeverywhere
RISC-V Mentorship Program

RISC-V Mentorship Program

Connecting developers with experienced mentors, providing hands-on learning opportunities and fostering collaboration.

riscv.org
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John Round (@openhwsw) profile picture
John Round@openhwsw8 May 2023
** 432-Core Chiplet-Based RISC-V Chip Nearly Ready to Blast Into Space #riscv lnkd.in/gfWAFbk5

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lnkd.in
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Chip design and development carries big budgets that come with a licensing fee for an ISA and core architecture. RISC-V is changing this dynamic by democratizing the chip design process while providing a modular path forward for new hardware. bit.ly/3LGteT9 #Cadence
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RISC-V International (@risc_v) profile picture
RISC-V International
@risc_v1 May 2023
.@risc_v CEO @Calista_Redmond will be giving a #keynote at this year’s Open Source Summit North America! Join us at #OSSummit from May 10-12 virtually and in Vancouver, Canada: hubs.la/Q01MYxs10 @linuxfoundation #RISCVeverywhere
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RISC-V International (@risc_v) profile picture
RISC-V International
@risc_v1 May 2023
Join #RISCV at @60thDAC! We will be showcasing the power of open collaboration at the #RISCVZone. @risc_v CEO @Calista_Redmond will also be moderating a panel with leaders from @Amazon, @ImperasSoftware, @Intel, @Meta, and @openhwgroup. Learn more: hubs.la/Q01MYH7s0
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