On-demand excerpts and the full replay from today's "Field-Programmable Gate Arrays and the #IEEE Milestone" #webinar will be available soon. Our thanks again to @ASU's Aman Arora, @UofT's Vaughn Betz, #UWaterloo's Andrew Boutros, and @IEEEorg's Michael Geselowitz. #FPGAWebinar

And here's a final summary of the key takeaways from today's @ProceedingsIEEE "Field-Programmable Gate Arrays and the #IEEE Milestone" #webinar. Our thanks to our expert speakers for a great presentation, and to everyone who attended. #FPGA #FPGAWebinar

Here's a look at how you can achieve the best of both worlds when you have a #FPGA fabric alongside a vector processor, courtesy of @ASU's Aman Arora. #FPGAWebinar

Next, the data movement must also be hardened. @ASU's Aman Arora has examples showing two different routed for accomplishing this goal. #FPGA #FPGAWebinar

So, how are FPGAs handling these demands? It starts with hardening arithmetic #DeepLearning needs, including adding very narrow multipliers and reduction in the DSP slice. #FPGA #FPGAWebinar

Our next speaker is @ASU's Aman Arora, who shares how and why #FPGA architecture follows its workloads. He also notes that #DeepLearning is accelerating specialization, and explains what #DL is demanding of chips. #FPGAWebinar

The third design style introduced by #UWaterloo's Andrew Boutros is #FPGA-specific accelerators. For binarized NN, the impression is that efficiency is improved, there are still some drawbacks. #FPGAWebinar

#UWaterloo's Andrew Boutros also has a great look at generating custom CNN hardware, and how performance is impacted. #FPGA #FPGAWebinar

The second designs style #UWaterloo's Andrew Boutros points to custom model-specific hardware. He notes that FPGA's spatial nature enable greater customization and better efficiency. #FPGA #FPGAWebinar

What are some of the applicable design styles? #UWaterloo's Andrew Boutros is walking us through a number of them, beginning with overlay architectures, including this example, Microsoft's Brainwave overlay. #FPGA #FPGAWebinar

We're now hearing from #UWaterloo's Andrew Boutros, who is giving us a look at which #DeepLearning use cases are best suited for FPGAs. He also calls diverse I/Os "an underrated superpower". #FPGA #FPGAWebinar

What of low power requirements? Here's how #SpatialComputing and data flows play into things. #FPGA #FPGAWebinar

How do you optimize for low #latency? With a well thought out on-chip memory organization design, says @UofT's Vaughn Betz. #FPGA #FPGAWebinar

When we talk about FPGAs and these requirements, what do we mean exactly? @UofT's Vaughn Betz has a good summary of each, including how programmable I/Os, massive parallelism, and low latency and power enable you to choose your precisions. #FPGA #FPGAWebinar

What's needed for #DeepLearning applications? Flexibility, low-latency, and low power are all top priorities, according to @UofT's Vaughn Betz. #FPGA #FPGAWebinar

Our next speaker is @UofT's Vaughn Betz, who notes that FPGAs are critical to #DeepLearning inference spanning a diverse array of applications, as shown here. #FPGA #FPGAWebinar

How many @IEEEorg Milestones are there currently? There are 305, going as far back as 1751 with Ben Franklin to more modern day advances. The #FPGA Milestone is actually #303 in the roster. You can learn more at the Engineering and Technology History Wiki. #FPGAWebinar

So, what is an @IEEEorg Milestone? Here's an overview, courtesy of #IEEE History & Heritage Sr. Director, Dr. Michael Geselowitz. He notes that Milestones recognize an event in history that are within IEEE's fields of interest. #FPGA #FPGAWebinar

All of the devices highlighted in Dr. Michael Geselowitz's presentation were application specific, but that all changed in 1984 with the filing of a key patent. It led to the rise of fabless companies and a $100 bn USD industry. #FPGA #FPGAWebinar

As @IEEEorg History & Heritage Sr. Director, Dr. Michael Geselowitz notes, it's important to understand the pre-history of #semiconductors and how we got to where we are now. This timeline shows key points in the journey. #FPGAWebinar