Inder Saini

this smells very bad. none of the claims make sense. > low voltage hits 80% mfu high mfu is easy if your peak flops is low > low voltage solves power bottleneck bleeding edge wafers is more scarce than power and it doesn't make sense to tape out lower perf chips on these wafers to save power if you want perf/$. the true bottleneck to frontier perf is max flops density to minimize going off die. power is the most fungible elastic commodity on earth > half voltage = quarter power presumably: 1. only matmul gates (~60% of die power) at half voltage. half voltage -> ~3x slower -> need ~3x more transistors, and their power leaks scale linearly. ~20% net savings at chip level 2. half voltage -> engineering complexity to fix timing violations + exponentially scaled soft errors (~20x). matmuls will randomly corrupt undetectably from bit flips (and drop model intelligence). > btc miners run at 3x lower V btc workload is hashing, so 1) error checking is literally in the problem 2) arithmetic intensity is like infinity so they don't care about packing flops density in single die unlike AI workloads. doesn't make sense to copy > GPUs get low MFU from thermals no, they get low MFU from mem bw and non-matmul ops. > CSM 5x lower latency than Blackwell 4000ns Blackwell nvswitch is 300ns? unless they are comparing their bare hardware to nvidia hardware + software. the whole product design tradeoffs don't make any sense from first principles and only makes sense if their initial "transformer asic" had some horrible power issue that they solved by undervolting and they had to respin the whole story for investor marketing. would love to be proven wrong if anyone from Etched wants to educate me :)