YRabbit

Did I already mention that those USB Wi-Fi adapters are elephant shit? My guess is that they overheat because their antenna is poorly designed, causing a large portion of the transmitter's energy to be reflected back; this triggers the protection mechanism, cutting off t

It really frustrates me that I can't use the built-in wireless on BSD, because I know that, in most cases, those USB wireless adapters are absolute elephant shit. This particular unit heats up to over 60 degrees Celsius. That’s hotter than the processor itself.

And here is what happens when my theories don't pan out: the DFF lacking a clock signal simply halts the entire process. Oh well, time to come up with some other hypotheses. It’ll work eventually, but I’m already nominating the #TangConsole60k as the most convoluted, twisted

The refinement involves testing one specific "spine"—SPINE27. It differs radically from the other 30 spines because its switching cell falls within a non-existent, empty area. In theory, I imagine it’s combined with the adjacent cell, but it’s not straightforward due to

Excellent! 15 DFFs scattered across different clock quadrants are up and running. One LED is dedicated to the "ticks" :) This example will be included in *apicula* once I finish refining it. #fpga#apicula

I wonder if this tree's fruit is tasty?

Due to the complex clock routing structure in TangConsole60k, I am creating a specific example using 16 D-type flip-flops (DFFs) distributed across independent sections of the chip So far, 10 flip-flops are being used: those in the bottom and those in the right section of the top

"Hmm, this is using a whole 6 kilobytes - that won't do; I'll try to shrink it." Working within very tight memory constraints isn't exactly unfamiliar to me, but it is something I'd somewhat forgotten about. And it's actually quite fun. :) #micropython

Gee! I finally found that missing wire :) #TangConsole60k has learned to use its clock. 😜 Adjustments: all the design's flip-flops are neatly placed in the bottom half of the chip, since I have no idea how to handle the clock in the top half.😉 #fpga#apicula