I have finally submitted my first tapeout to wafer.space run2 shuttle Its a Dual core Risc V based IO co-processor based on BIO Co processor from Andrew "Bunnie " 's Baochip- x1 Basically : Two PicoRV32 RISC-V cores, 4 KB of foundry SRAM across 8 hard macros, 32 bidirectional GPIO, clock gating, and an SPI slave interface ,all in a half-width die slot (1936 × 5122 µm). Check it out : #riscv #opensource #silicon #asic

Chip #1 on this list, our single-core CORDIC from Tiny Tapeout, works. Just not at the SPI speed we planned. In mode 0 it tops out at 5 MHz. Here's why. The SPI slave was an oversampling design. SCK, MOSI and CS were sampled by the system clock through synchronizers, and edges were detected in logic. It's simple and it keeps everything in one clock domain. The cost is latency. Every SCK edge takes 2–3 system clocks to reach the logic. In mode 0 the slave updates MISO after the falling edge, and the master samples it on the next rising edge. All of that latency, plus pad and I/O delay, has to fit in half an SCK period. So the max SCK isn't set by how fast the logic is. It's set by the ratio to the system clock and the round trip through the pads. On Tiny Tapeout, that path also runs through the shared I/O mux. What I'd do differently: clock the shift register directly from SCK and cross into the system domain once per word. Or at least write the SCK-to-sysclk ratio into the spec on day one, instead of discovering it on the bench.

Its hard to see AI do my job better then me need to get serious skill upgrades , but model will become better as well so what to do now ? 🙁

And yeah this is die shot of the second chip that i have in wafer.space

Haven't done any side project from a long time should do something 😶.

Lessssssss go .

What if i make a opensource #riscv controller with a #tinygpu or a small #tpu embedded with it and tape-out on wafer.space . Would you be interested in getting your hands on one ?? Off course you will have to pay 🥲

The thing i understood about Chip design is that its not that hard its just crazy expensive 🙃.

SO someone cited my sloppy paper. Dayum

The amount of things I have tried , learnt and got done in last 2 years . If I put it on my resume people would thing I am lying. Perks of working in a startup I think. 😶

Ahh I forgot we already made it .

Random dump from semicon taiwan 🤓

Surat also have a lot of such park of-course they are smaller then this but well maintained.

yeah so me your superlint report. 😢

The bio core that i worked and submitted to wafer.space run2 is finally in silicon and we can also see the cute 👻 PC: Andrew Wingate from wafer.space

We bee printing 🤓