AMD’s latest CPU 9950X3D2 is getting many talking about the penalties of cross-CCD cache latency. But trust me, AMD has a way weirder chip, the EPYC 9175F. At first glance, they look *somewhat* similar. Both 16 cores, 32 threads, Zen 5, lots of L3. Yet, the EPYC spreads it across 16(!) CCDs! It is an absolutely bizarre CPU. Essentially the same topology as the 128-core EPYCs, but with 7 cores disabled on every chiplet! Honestly a nightmare for synchronized multithreaded code, because communicating between ANY core means you’re crossing CCDs. So, that cross-cache latency that everyone complains about on the X3D2 is ridiculously amplified. So what is it good for? There’s probably ~2 good reasons. One would be software that uses per-core licensing. The other would be any time you need low latency independent threads…with as much *local* L3 as possible. Not all L3 is created equal! The X3D2 might have big, total slices of L3…but that takes about a 4 cycle V-Cache penalty. With the 9175F, each core has 32MB of local, uncontended L3 with no penalty. It’s actually a pretty neat chip if you can fit your working set into ~32MB!