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Thanks to Jon, who managed to dig up the microcode listing from the TI archives, I can finally resume work on the TMS7000 core! 71 CPU instructions already pass tests on the Verilog core (31.3%) @guidryjd 🙏

I just received and scanned the Shoot Out service manual. Full schematics included🙂 I'll start the core development in the coming days.

This is the second game I worked on this summer. Still a few issues (sound, obj priorities), but the core is running nicely. AI helped a lot on this one, but as my colleague said: "any AI still needs a capable person behind it", so I feel less guilty now🙂

It's been a while since my last core release! Ring King arcade core for #MiSTerFPGA is now available.

I restarted my work on MiSTer cores and immediately fell right back into the exact same silly trap: leaving interrupt lines disconnected 😅 After I connected the int line, sound is finally here on RingKing.

It started with MAME ports 😬, and now we're getting MAME ports made by Fable... 😬😬

This is so cool! Thank you @Pmaxsd

I used to think we needed broad knowledge to build custom tools when porting hardware to FPGA. Now, with AI, a few prompts give us everything we need🙃

Thanks to the kindness and professionalism of the staff at the DeGolyer Library @SMU_Libraries, I finally gained access to scans of the TMS7000 Microcode Development Guide from the Texas Instruments archives! 😀

I try to rebuild the TMS7000 microcode ROM, mostly guesswork😒Frustrating that the listing exists in TI’s archives but hasn’t been scanned yet...

It seems one of these documents might contain the full source code of the TMS7000 microcode. Does anyone know where I can find the microcode listing? - TMS7000 Micro-architecture - TMS7000 Microcode Development Users Guide - TMS7000 Micro Assembler

I spent several weeks working on a RISCV32 CPU, and now I can boot Linux! 🙂 It's just a software simulation for now.

Another technical detail about Pandora's Palace: they set the four upper bits of DX bus (sprite X/Y) to high impedance (COL signal) to insert the H/V flip flags from DC in time (blue), ensuring the Konami 503 captures them correctly, since the attribute byte never reaches it.

Pandora's Palace has 24 hardware sprites, but the title screen shows up to 38 sprites at once. This is possible thanks to the Konami 85 scroller chip, which has a vertical read pin. The CPU uses it to track the scanline position and reuse the slots of already rendered sprites.

End of vacation, time available for MiSTer = ε 😭

I'm rewriting some of my guesses with better chip implementations. I'm working on the Konami 504, which is mainly a 6809 E/Q clock divider. I'm only writing HDL, someone else reversed it. It seems to work! 😊

I hooked up PROM and fixed values for the color resistors. I need to look at sprite decoding now.

Just got the first screen of my little summer FPGA core project, coded on my phone at the beach🩴🏖️

In a recent discussion with @s_on_vg about arcade backbuffer techniques, we discussed the following methods: DMA, pointer swapping, and memory swapping. Did we forget any?