Deep-Tech Semiconductor Analyst, MSEE @JohnsHopkins. Expert-driven system architecture deep-dives of AI datacenter hardware at https://xitter.cf/t.co/atebRcUn6C
Austin, TX
Joined April 2025
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Chad Wallace retweeted
Ken Griffin of Citadel questions the economics of the AI infrastructure boom:
›What happens when GPU supply exceeds demand & pricing goes into free fall?
›Are today's semiconductor margins sustainable? Are investors overestimating the useful life of GPUs?
“Look, I think this market is actually experiencing people doing research.
For the couple of years, if you were on the thematic program of we're gonna spend hundreds of billions or a trillion dollars in data centers, we're gonna build compute at a scale never seen before, which companies in that story are choke points in supply chains that will have abnormally high margins? And who will be the big winners in this transformation?
Will it be the Microsofts & AWSs who will be the gatekeepers to the foundational models? Like, who's going to earn the economic rents?
But in some sense, like, 'I'm just gonna buy them all. I'm gonna buy the hyperscalers, I'm gonna buy the chip, I'm gonna buy businesses that make things I've never even heard of 5 years ago in Korea and Taiwan & in Japan.'
And now we're reaching a point where people are becoming more discerning.
We do realize that we are seeing extremely high margins in DRAM & MLCCs in areas where there are real supply constraints, but people are now starting to look out 2 years, 3 years. How long is this going to last?
And in particular, I don't wanna be doom & gloom, but GPUs, like airlines, have a very low marginal cost to run.
The incremental seat on an airline that's not full, if you can sell that ticket for $20, you're making money in that seat.
And that's one of the reasons that the airline industry is such a nightmare, is because the moment you have overcapacity, pricing goes into free fall.
We saw this actually with the telecom build-out back in 2000. We built more fiber than we had demand for, & the price of telecommunications just went straight down.
If we reach a point where the provisioning of GPUs exceeds demand for GPUs, marginal pricing will actually go into free fall.
And that really upends all the investment assumptions that people are working with today.
That's issue number one.
And issue number 2 is:
I think people are taking a step back & saying, 'What is the useful life of a GPU?'
Right here, right now, there's people that are earning extraordinary pricing on GPUs that are 5 or 6 years old.
And so there's a growing set of concerns that I can't give the same capitalization rate or the same revenue models to year 7, 8, 9 of a chip in the future that maybe I was using 12 months ago.
So I think we're really grappling with just how far will this demand carry us in the marketplace.”
Chad Wallace retweeted
AI infrastructure has reached the point where SpaceX wants to manufacture gas-turbine blades because the existing supply chain is too slow.
That sounds almost absurd until you look at the physical stack underneath a large AI cluster. You can have the land, GPUs, servers and customer demand lined up, then wait on transformers, switchgear, turbines or other equipment required to turn a site into usable megawatts. U.S. utilities are already dealing with transformer lead times that can stretch past three years, and SpaceX says bringing turbine-blade casting in-house could accelerate turbine deployment by as much as 18 months.
The blade itself is also a great example of why these constraints are difficult to brute-force. High-performance turbine blades can involve single-crystal nickel superalloys grown in vacuum furnaces. A tiny defect can scrap the part, specialized furnaces themselves can have multi-year lead times, and only a small group of manufacturers has mastered the process at scale. GE Aerospace’s $11.75 billion deal for Consolidated Precision Products this week is another signal that control of this supply chain has become strategically valuable.
I think investors are still mentally modeling AI infrastructure as a semiconductor supply chain. but from my pov it's increasingly looking like an industrial supply chain with semiconductor economics sitting on top.
That creates a much more interesting question than “who gets the GPUs?” Which obscure component has enough leverage to strand $5 billion of GPUs when that component shows up six months late?
Chad Wallace retweeted
SiPh is now ready for ramp up by seeing PKG
- ficonTEC positioned itself at ECOC 2026 as transitioning from custom-build to scalable production of photonics assembly and testing equipment.
- Company emphasized that scaling photonics requires stable processes, precision alignment, effective testing, and improved yield, not just speed increases.
- ficonTEC offers integrated solutions across fiber preparation, precision assembly, active alignment, and electro-optical testing under one organization.
> ficonTEC's emphasis on scalable, integrated manufacturing solutions across the photonics assembly chain addresses a critical bottleneck in AI infrastructure and next-generation optical packaging, where the industry is transitioning from prototype to volume production capabilities.
Chad Wallace retweeted
Most important point, IMO, from the CPO summit at AI infra is for optics to scale, no single source, nor no single solution is likely. All forms of optical interconnect are likely to be used to meed the demands of scale up (intra and inter rack), scale out, and scale across.
Chad Wallace retweeted
Lots of discussion about FP formats with David Patterson (@FelixCLC_ name checked by @IanCutress )
Chad Wallace retweeted
I run a community of around 1,000 industry professionals working in Silicon Valley and around the world.
Our members work across optics, semiconductors, AI, and many other fields. @NuttyCLD, @PhotonCap, and @SVTrivo are three fantastic people I’ve met through this community.
I plan to have more conversations with these experts and turn their insights into accessible articles that explain the technologies and industries they work in.
Here are the expert calls currently planned:
• Intel Foundry Research Engineer (Done)
• Samsung HBM Packaging Engineer
• ASML Research Engineer
• AWS AI Research Engineer
• Micron HBM Product Engineer
If there are other companies you’d like to hear about, leave a comment. I’ll see what I can arrange.
Thank you!
Note: These interviews will focus on publicly available information and general technical knowledge. I will not discuss confidential or nonpublic company information.
Today, I had an expert call with an $INTC Foundry professional from my semiconductor industry community.
It was a great opportunity to gain a deeper understanding of Intel’s technology, current position, and vision for the future.
Going forward, I plan to publish more articles based on my conversations with experts across AI and semiconductors.
The first one will be available soon, so stay tuned and visit my Substack!
Chad Wallace retweeted
Yay, in TIME100 AI w/ @Azaliamirh !
With AlphaChip, we started the field of AI for Chip Design.
Last year, we founded Ricursive to take on all of chip design, from model to GDS (the final input to the fab).
How we got here: (1/n)
Chad Wallace retweeted
Hey people @hotchipsorg, can you only ask one question when you go up to the microphone? Having a multi-parter each with three sections isn't cool!
Chad Wallace retweeted
Published in Nature Electronics, a new paper from @SKhynix and University of Virginia researchers explores how CPO can overcome the “bandwidth wall” through optical connectivity.
🔗 Read the full story below.
news.skhynix.com/en/cpo-in-n…
#SKhynix #CPO #AIInfrastructure
Chad Wallace retweeted
One of my long-standing critiques of Silicon Valley has been that it holds a religious belief that all the world's problems can and will be solved by computer scientists (which is why also imo SV has held a slightly elevated sense of self-importance and, frankly, inward-looking)
While it is true that discoverable alpha in computer science is diminishing/has become fully saturated, the next frontier is explicitly in hard sciences (which tbf may leverage advances in compsci), which does present a lot of opportunity for extremely "technical" or "scientific" co-founders. It's just not the "technical" co-founders SV has become accustomed to
Chad Wallace retweeted
AI-native, agent-native EDA tools that enable fast, efficient chip design and debug; mission: spec-to-freeze-ready RTL in three months.
semiwiki.com/eda/371696-ceo-…
Chad Wallace retweeted
$SVCO is integrating $NVDA accelerated computing and AI with its physics-based simulation portfolio to advance digital twins for semiconductor design and manufacturing
Potential applications include semiconductor process, device, packaging and photonics simulation, as well as fab visualization, predictive manufacturing, robotics and factory optimization. Silvaco aims to reduce some simulation cycles from weeks to days.
--> Accelerating workloads on GPUs that are impractical on CPUs is not new. What makes this announcement interesting is Silvaco’s attempt to combine its existing TCAD and simulation portfolio with NVIDIA’s accelerated computing and AI-based digital-twin technologies, potentially expanding further into photonics.
The 3.2-billion-node mesh also suggests that memory capacity and bandwidth were likely key bottlenecks. This highlights that, in photonics simulation as in AI, memory systems increasingly determine both performance and the scale of solvable problems. It will be interesting to see whether Silvaco can turn this into meaningful competitive pressure on Ansys ($SNPS).
Chad Wallace retweeted
Sitting next to Dr. Wally Rhines and @timothybcosta ahead of the DAC pre show - AI Meets EDA: The Future of Chip Design
Chad Wallace retweeted
Right before SK Hynix execs take the stage, Pat Gelsinger calls HBM their flagship product "a lousy memory" that wastes four bits for every one it makes.
"We've heard about HBM, high bandwidth memory. And HBM is a lousy memory. And I know my memory friends are about to come on stage, and calling their baby ugly is not maybe the best way to make friends and influence people. But it's a lousy memory."
"You're stacking DRAM. DRAM doesn't like to be stacked, because essentially you're creating a thermal sandwich. That's bad. It's shoreline-bandwidth limited, so essentially I'm trying to get bandwidth through this point-to-point connection between the memory and the GPU, so I have bandwidth limitations associated with it."
"And it is bitwise inefficient: for every bit that I'm creating for HBM, I've given up four bits of memory, nominally. So it's bit-inefficient, power-inefficient, and bandwidth-inefficient. It is just the best one we have right now."
Chad Wallace retweeted
If you're in software, pivot into hardware.
The biggest opportunity in the coming decade is on putting intelligence into a physical device.
Robots, drones, autonomous vehicles, industrial automation, medical devices, energy systems, wearables: each needs engineers who understand electrons, not just abstractions.
Software gives leverage. Hardware gives the ability to actually ship the machine. Together they compound.
Chad Wallace retweeted
Optical networking is already widely used for scale-out connections across data centers, while low-latency scale-up links between GPUs inside a rack still rely primarily on copper technologies such as NVIDIA NVLink.
As signaling speeds increase, copper links face greater attenuation, power consumption, and heat. NVIDIA plans to expand its tightly connected systems from 72 GPUs today to as many as 576 by 2027, and the company acknowledges that in-rack copper is approaching its physical limits.
NVIDIA’s NVLink Fusion ecosystem now includes photonics companies such as Ayar Labs, Marvell, and Lightmatter. Ayar Labs is developing optical chiplets positioned beside processors, while Lightmatter is pursuing photonic interposers that can sit underneath compute chips.
Improvements in foundry processes, hybrid bonding, packaging, and testing have made co-packaged optics more manufacturable. However, integrating large numbers of lasers efficiently and reliably remains a major challenge.
NVIDIA is taking a gradual approach, adopting optics first in scale-out networks and potentially extending it into scale-up systems as bandwidth requirements increase. Industry participants expect multiple high-volume optical scale-up implementations around 2028, although this remains a forecast and copper is likely to coexist with optics for some time.
--> Optical scale-up is being pursued through a wide range of architectures by multiple companies and engineering teams. Ayar Labs is developing optical chiplets, while Lightmatter is taking a photonic-interposer approach, and other implementations will continue to emerge. At this stage, predicting the eventual architectural winner is difficult. A more useful strategy is to focus on the common bottlenecks and chokepoints that every solution must pass through.
As I have consistently argued, the two most critical layers in silicon photonics and co-packaged optics are packaging and measurement/testing. Optical devices, electronic chips, lasers, and fibers must be integrated with low loss, high yield, and sufficient reliability. Once assembled, both individual components and complete optical engines must also be tested at production speed and scale. As competition between architectures intensifies, these two layers are likely to determine which technologies can actually reach high-volume manufacturing.
