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Atomic Rules (@AtomicRules) profile picture

Atomic Rules

@AtomicRules

Enterprise-Grade FPGA IP Cores and Solutiion

 New England
atomicrules.com
Joined December 2014
  • Tweets238
  • Following69
  • Followers228
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Photo by Atomic Rules (@AtomicRules)Photo by Atomic Rules (@AtomicRules)Photo by Atomic Rules (@AtomicRules)Photo by Atomic Rules (@AtomicRules)Photo by Atomic Rules (@AtomicRules)Photo by Atomic Rules (@AtomicRules)Photo by Atomic Rules (@AtomicRules)Photo by Atomic Rules (@AtomicRules)Photo by Atomic Rules (@AtomicRules)Photo by Atomic Rules (@AtomicRules)
Glad to have another IP/Solution entry from @AtomicRules with TK242, a 200G lossless capture solution using BittWare PCIe cards and @IntelFPGA Agilex™ FPGAs! bittware.com/ip-solutions/at…
Image from Molex Rugged/Enterprise/Microelectronics (@BittWareInc)
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Missed our @AtomicRules Arkville webinar (220 Gb/s PCIe Gen4 x16 data mover on @IntelFPGA Agilex)? It's now available now on demand (including the recorded Q&A): bittware.com/resources/webin…
BittWare Accelerator Boards, PCIe Cards, and Integrated Systems Featuring Achronix, Altera, and AMD...

BittWare Accelerator Boards, PCIe Cards, and Integrated Systems Featuring Achronix, Altera, and AMD...

BittWare provides enterprise-class FPGA hardware and integrated systems featuring technology from AMD, Altera, and Achronix. Accelerate your network, storage, and compute solutions with low-risk,...

bittware-molex.com
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Atomic Rules retweeted
Altera (@AlteraFPGA_) profile picture
Altera
@AlteraFPGA_13 Dec 2021
Join our webinar 16:00 UTC / 11:00 EST, Tuesday 14th December to hear Bittware, Intel, and Atomic Rules experts provide details of the products used achieve reduced time to market and easier development without sacrificing performance. intel.ly/3IF1eeJ
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Atomic Rules retweeted
Satnam Singh (@satnam6502) profile picture
Satnam Singh@satnam65022 Jun 2021
I gave my final lecture on the UC Santa Cruz CSE-125/225 Verilog hardware course. Of course, it was on Bluespec using the "classic" original Haskell syntax, so the students can see a totally different way of thinking about hardware specification and design. @bluespec
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Atomic Rules retweeted
Jan Gray (@jangray) profile picture
Jan Gray@jangray1 Apr 2020
Dear friends, With deep regret we must share the terrible news that our friend and colleague Mike Butts @KC7IT passed away on Sunday, March 29, 2020.
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Open source hardware design gaining momementum! Production proven BSV tools with 20 year investment to be released this month. bluespec.com/2020/01/06/blue…
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Startup creates new tools to let FPGA programmers fly buff.ly/2AT6MlH #FPGA #startup
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Atomic Rules retweeted
DPDK (@DPDKProject) profile picture
DPDK@DPDKProject27 Sep 2017
Our #DPDK Open Lab work is coming along thanks to work by @mellanoxtech @AtomicRules @intel & @NXP. Community Collaboration! #DPDKSummit
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Atomic Rules retweeted
DPDK (@DPDKProject) profile picture
DPDK@DPDKProject3 Apr 2017
Our Silver members include @6WINDsoftware, @AtomicRules, @Huawei, @Spirent, & @WindRiver. linuxfoundation.org/announce… #ONS2017 #DPDK #SDN #NFV
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Atomic Rules retweeted
Jan Gray (@jangray) profile picture
Jan Gray@jangray7 Sep 2016
#FPGA 400 MHz timing closure practice & experience: @AtomicRules' at Club Vivado dl.dropboxusercontent.com/u/… (new link) teapawt.net/jangray/status/6678424…
Jan Gray (@jangray) profile pictureJan Gray@jangray20 Nov 2015
#FPGA Shepard Siegel @AtomicRules: Tackling 400 MHz Timing Closure for 25/50/100 GbE japan.xilinx.com/publication… :-)
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Atomic Rules retweeted
Jan Gray (@jangray) profile picture
Jan Gray@jangray25 May 2016
When these parts available, FPGA workloads won't have to suffer for low DRAM BW.
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BittWare and @AtomicRules announce an #FPGA-based UDP Offload Engine IP Core for ... design-reuse.com/go2/439726/… #semIP
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When future kids ask their tech-savvy parents where they met
Image from Sara Soueidan is on Bluesky (@SaraSoueidan)
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Atomic Rules retweeted
Jan Gray (@jangray) profile picture
Jan Gray@jangray8 Nov 2015
#FPGA The soft processor perf metric I chase is millions of instructions per second per LUT (MIPS/LUT). #JansRazor fpgacpu.org/log/mar02.html#0…
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Atomic Rules retweeted
Jan Gray (@jangray) profile picture
Jan Gray@jangray23 Feb 2015
#FPGA #FPGA2015 Much interest in MS Catapult. research.microsoft.com/catap… "How will you use Catapult?"
Image from Jan Gray (@jangray)
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#Xilinx #UltraScale architecture + TSMC’s 16FF+ process = #16nm UltraScale+ All Programmable Devices (24 new devices) bit.ly/1LwLFQD
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Atomic Rules retweeted
Jan Gray (@jangray) profile picture
Jan Gray@jangray23 Feb 2015
#FPGA @XilinxInc UltraScale+ UltraRAM: new larger on-die SRAM memory block. Fewer BRAMs/LC. Total SRAM bandwidth +/-?
Image from Jan Gray (@jangray)
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Atomic Rules retweeted
Jan Gray (@jangray) profile picture
Jan Gray@jangray23 Feb 2015
#FPGA #FPGA2015 "1 FP DSP = 1 FX DSP + 700 LUTS -- typical system savings of 85-90% soft logic"
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