FPGA Design Engineer. Working to improve the state of digital logic design: https://teapawt.net/t.co/ATqFxRT3OZ ( INACTIVE. PLEASE EMAIL: [email protected] )
Joined November 2009
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I'm writing an online book: "FPGA Design Elements",
which provides a reference library of fundamental digital logic design elements. Think of it as a hardware analog to the C Standard Library ("libc") and its documentation.
fpgacpu.ca/fpga/index.html
github.com/laforest/FPGADesi…
#FPGA
I'm not monitoring this account for now.
Please email me at: [email protected]
Or find me at fpgacpu.ca/
Here's a common workhorse for designs: a Pipeline FIFO Buffer. Any FIFO depth is allowed, not only powers-of-2. The input-to-output latency is 2 cycles. Can function as a Circular Buffer. The tricky bit is the read output, which is registered for speed.
fpgacpu.ca/fpga/Pipeline_FIF…
A Pipeline Half-Buffer: A single pipeline register with ready/valid handshakes. Decouples the input and output handshakes (no combinational path), but does not allow concurrent read/write like a full Pipeline Skid Buffer.
fpgacpu.ca/fpga/Pipeline_Hal…
Here's the most important pipeline building block: a Skid Buffer. It decouples two sides of a ready/valid handshake to allow back-to-back transfers without a combinational path between input and output, thus fully pipelining the path.
fpgacpu.ca/fpga/Pipeline_Ski…
As I struggled today with an FPGA CAD tool's IP code generation and management, it occurred to me that I haven't needed to write HDL-generating code for years now. Modularization, along with generate blocks and parameters, has always sufficed, even for 20k+ line designs.
Charles Eric LaForest, PhD retweeted
Clock stability is essential: with a 1 GHz clock you get 1ns on your critical path to close timing. But if your clock's 99.9999999999th percentile shortest period is even just 10% shorter then you *must* get everything done in 900ps, or your circuit will fail within an hour.
Here is a module which extends the 1-to-N Differential Deserializer by packing two consecutive differential N-bit deserialized words into one differential 2N-bit word and extending the bitslip word-alignment logic to support this double-width word. fpgacpu.ca/fpga/Deserializer…
When aligning multiple data channels, you need to pass them through variable-delay shift registers. This is where using an FPGA's built-in shift-register hardware is a must, since using LUTs+FFs ends up being the large majority of the deserializer area!
fpgacpu.ca/fpga/Register_Pip…
A pipeline serial to parallel converter. Reads in multiple serial words and signals when the last input word has been read-in and a new, wider output word is ready to be read-out, in the same cycle if necessary to receive an uninterrupted serial stream.
fpgacpu.ca/fpga/Pipeline_Ser…
A deserializer for differential data, with a configurable 1:N ratio, SDR or DDR data rate, and independent positive and negative data polarity input delays and deserializers, which enable bit and word alignment training later on.
fpgacpu.ca/fpga/Deserializer…
An IDELAYCTRL instance for calibrating IDELAY2 blocks. This is the first step to high-speed interfaces on Series 7 AMD/Xilinx FPGAs.
fpgacpu.ca/fpga/IDELAYCTRL_I…
fpgacpu.ca/ now supports HTTPS! It's still a static site without cookies or Javascript or any inputs, but I was getting reports of problems with browsers, corporate networks, and Google not liking the absence of SSL. Enjoy more easily now!
I have an open slot for a client at this time.
Let's discuss your FPGA design needs! fpgacpu.ca/gateforge/index.h…
I'm a consultant doing primarily logic design on FPGAs and related software development for clients who need application-specific processing for their products.
I have an open slot for a client, starting *immediately*. Let's discuss your FPGA design needs! fpgacpu.ca/gateforge/index.h…
I'm a consultant doing primarily logic design on FPGAs and related software development for clients who need application-specific processing for their products.
In one project, I had to first configure an external device before it could generate it's own source-synchronous clock for data. This Clock Switchover module detects when the device data clock is active and stable and handles clock selection and reset.
fpgacpu.ca/fpga/Clock_Switch…
I have an open slot for a client, starting in the last week of July. Let's discuss your needs! fpgacpu.ca/gateforge/index.h…
I'm a consultant doing logic design on FPGAs and related software devel (from kernel up to application) for clients who need application-specific processing.
We can now build a saturating accumulator with variable upper/lower limits. I used this as the Integral term of a PID controller, with dynamically adjusted limits to limit integral wind-up, which makes the PID controller recover from saturation faster.
fpgacpu.ca/fpga/Accumulator_…
Here's a Saturating Adder/Subtractor. The limits are any signed numbers, even dynamically variable. One use is as the final stage of a PID controller, so we can guarantee the output never wraps around and flips sign suddenly, which would be catastrophic.
fpgacpu.ca/fpga/Adder_Subtra…
With an Subtractor, we can create an Arithmetic Predicates module which computes all possible signed and unsigned comparisons of two numbers. This way we don't have to worry about getting RTL arithmetic right each time.
fpgacpu.ca/fpga/Arithmetic_P…
And with those previous modules, we can now build an adder/subtractor module. It's much more complex than usual, but it also gives us all bit carries and the overflow bit, and is independent of Verilog's signed/unsigned arithmetic behaviour.
fpgacpu.ca/fpga/Adder_Subtra…