FPGA Design Engineer. Working to improve the state of digital logic design: https://teapawt.net/t.co/ATqFxRT3OZ ( INACTIVE. PLEASE EMAIL: [email protected] )
Joined November 2009
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Charles Eric LaForest, PhD retweeted
Clock stability is essential: with a 1 GHz clock you get 1ns on your critical path to close timing. But if your clock's 99.9999999999th percentile shortest period is even just 10% shorter then you *must* get everything done in 900ps, or your circuit will fail within an hour.
Charles Eric LaForest, PhD retweeted
Unfortunately, the free Vivado 2024.1 license won’t support any Versal devices, despite the free AIE-ML compiler. A paid license is required for VE2302 dev boards, hindering Versal adoption in hobby, education, or crowdsupply projects. Altera wins with the free Agilex 5 license.
Charles Eric LaForest, PhD retweeted
A sometimes overlooked metric in Xilinx #FPGA designs is the number of unique control sets—a control set being defined as the combination of a clock, a clock-enable and a reset signal. Too many control sets prevent the efficient packing of logic into slices.
Charles Eric LaForest, PhD retweeted
A public service reminder to always keep your #FPGA logic under reset while its clock-generating circuit (PLL or MMCM) is not locked. This is especially important for stateful logic like FSMs.
Charles Eric LaForest, PhD retweeted
Looking for an FPGA dev board? I've just put together a comprehensive list and categorized the boards according to a few useful features lnkd.in/ewhANnUT
Charles Eric LaForest, PhD retweeted
I've updated my list of HDL code checkers/lint tools. Anything missing?
airhdl.com/blog/2017/02/08/f…
Charles Eric LaForest, PhD retweeted
#FPGA tip: in @XilinxInc Vivado, you can use the create_generated_clock command to give generated clocks more descriptive names, e.g. create_generated_clock -name clk_50mhz [get_pins {inst_dds_clk_pll/inst/plle2_adv_inst/CLKOUT1}]
See also UG903 "Renaming Auto-Derived Clocks"
Charles Eric LaForest, PhD retweeted
The @XilinxInc Y2K22 bug
support.xilinx.com/s/article…
Charles Eric LaForest, PhD retweeted
nMigen is now called Amaranth HDL!
follow it to its new home at github.com/amaranth-lang and the #amaranth-lang IRC channel on libera.chat
Charles Eric LaForest, PhD retweeted
😺Day 6: YosysHQ Founded
No one has done more for open-source FPGA than @oe1cxw. This year, Yosys, nextpnr, SBY, and Project IceStorm found a safe new home at YosysHQ.
I can't wait to see what the YosysHQ team have in store for 2022.
YosysHQ Tools: yosyshq.com/open-source
Charles Eric LaForest, PhD retweeted
I just released a major update of my online video timings calculator tool.
New features:
- CEA-861
- DMT
- Sync polarity
- Modeline generation
- A bit easier on the eyes
Check it out here: tomverbeure.github.io/video_…
ALT Screenshot of video timings calculator webpage.
Charles Eric LaForest, PhD retweeted
I'm excited to announce that you can now purchase our products from @digikey!
Charles Eric LaForest, PhD retweeted
Embedded systems tip: before coding anything, always check your clocks using an oscilloscope and/or a spectrum analyzer. This just takes a few minutes of your time and can save you a lot of trouble down the road.
Charles Eric LaForest, PhD retweeted
This beautiful clear and sunny afternoon in Portland we are gathering to remember and celebrate our friend and colleague Mike Butts @KC7IT.
A pioneer and an uplifting leader in our field of computing with FPGAs.
youtu.be/l5p4VHPbVIk
Charles Eric LaForest, PhD retweeted
The "premature" in "premature optimization" means "Before you fully understand the problem." This is also the loophole that makes it okay for a domain expert to sometimes optimize from the get-go.
